Accompanied with the recent trend for a higher integration or higher performance of LSIs, the reduction of the power consumption has been recognized as an important problem. Specially, in the CMOS LSI, the power consumption is proportional to the square of the power supply voltage, and accordingly, decreasing the power supply voltage can be the most effective method for reducing the power consumption of the LSI. However, decreasing the power supply voltage leads to decreasing the operation speed of the MOS transistor. In order to avoid this, the threshold voltage in the active mode is needed to be reduced; however, the reduction of the threshold voltage leads to the increase of leakage current of the MOS transistor in the standby mode. As an LSI to solve such a problem, an MTCMOS (Multithreshold-Voltage CMOS) has been proposed. The MTCMOS is presented, for example, in the study: "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS (IEEE JOURNAL OF SOLID STATE CIRCUIT. VOL. 30. NO. 8, AUGUST 1995)".
In general, this type of MTCMOS is connected between a virtual power supply line and a virtual ground line. It is comprised of logic circuits of MOS transistors having a low threshold voltage, and standby power control MOS transistors having a high threshold voltage, which are connected between the power supply line and the virtual power supply line and between the ground line and the virtual ground line, in order to reduce the leakage current of the MOS transistors in the standby mode.
However, since the threshold voltage of the standby power control MOS transistors used for reducing the leakage current in the standby mode is set sufficiently high, the virtual power supply line VVDD or the virtual ground line VGRD is not supplied with a sufficient current in the active mode. In consequence, the MTCMOS is not able to achieve a high-speed logic operation, which is disadvantageous.